In an integrated semiconductor memory device, for example a DRAM (Dynamic Random Access Memory) semiconductor memory, the memory cells are arranged in a matrix-like memory cell array, the matrix-like shape of the memory cell array being obtained from the essentially vertically running word lines and horizontally running bit lines. During access to a memory cell, the memory cell is conductively connected to one of the bit lines by an appropriate signal on the word line. At the end of the bit line there is a sense amplifier which detects the cell signal transmitted via the bit line and amplifies it. The amplified signal is first written back to the cell via the bit line and can then be read to the outside. This process takes place simultaneously for all memory cells which are associated with a word line. This means that, after a word line has been activated, all of the bit lines within the memory cell array have a signal applied to them.
To make the arrangement of the memory cell array as compact as possible, it is desirable to have bit lines which are as long as possible. On the other hand, however, this results in a reduction in the signal that the sense amplifier can detect. The memory cell area of an integrated semiconductor memory device is therefore generally split into individual memory cell arrays. FIG. 1 shows a memory cell area 10 in an integrated semiconductor memory device which is split into the memory cell arrays B1, B2, B3 and B4. Between the individual memory cell arrays, the sense amplifiers run in a sense amplifier strip SFa, a sense amplifier strip SFb and a sense amplifier strip SFc. In the memory cell arrays B1 and B2, respective horizontally running bit lines BL and, running vertical thereto, word lines WL1 and WLr are shown. Pairs of bit lines are respectively connected to sense amplifiers in the sense amplifier strips SFa and SFb, respectively.
To obtain an arrangement for the memory cell array which is as compact as possible, the sense amplifiers are used to amplify signals on a bit line in the first or second memory cell array, depending on the activated word line. A single sense amplifier can thus be used to access either a memory cell in the first memory cell array B1 or a memory cell in the second memory cell array B2.
To clarify this central idea behind the sense amplifiers, FIG. 2 shows an enlarged view of the block SSA, shown in dashes in FIG. 1, in the memory cell area 10. The sense amplifier SA, which is in the sense amplifier strip SFa, is respectively connected to a bit line BL and to a complementary bit line /BL in the first memory cell array B1 and in the second memory cell array B2. In FIG. 2, the bit lines BL in the first and second memory cell arrays B1 and B2 each have a DRAM memory cell connected to them, for example. The DRAM memory cell contains a selection transistor AT whose controllable path is connected to the first electrode of a storage capacitor SC. The second electrode of the storage capacitor is connected to a reference potential M. The selection transistor AT of the memory cell SZ in the first memory cell array can be controlled using a control signal on the word line WL1. The selection transistor of the memory cell SZ, which is in the second memory cell array, can be actuated using a corresponding control signal on the word line WLr.
To read cell information which is stored in the memory cell, the selection transistor is switched to the conductive state by applying the control signal. The charge stored on the storage capacitor SC flows via the controllable path in the selection transistor AT to the bit line BL and alters the potential thereof. The sense amplifier SA connected to the end of the bit line amplifies a fall in potential or a rise in potential on the bit line, depending on the stored cell information. The sense amplifier ensures that, by way of example, in the case of a fall in potential on the bit line BL, a low voltage level VBLL is applied to the bit line BL. Conversely, a high voltage level VBLH is applied to the complementary bit line.
When reading a memory cell SZ, which is in the first memory cell array B1, it is necessary to turn on the switching transistor ISO1 or ISO2, which connects the sense amplifier SA to the bit line BL or to the complementary bit line /BL. To this end, the control signal MUXr is applied to the control connection MAr of the two switching transistors. If it is necessary to read a memory cell in the second memory cell array B2, the sense amplifier SA is connected to the bit line BL or to the complementary bit line /BL in the second memory cell array by means of the switching transistors ISO1 and ISO2, respectively, arranged in the second memory cell array. In this case, the control signal MUX1 is applied to the control connection MA1 of the switching transistors in the second memory cell array B2 and turns on the two switching transistors.
As can be seen from FIG. 1, the word line WLr or WL1 in the first or second memory cell array is connected to all bit lines which are present in this memory cell array. This means that when a word line is activated, for example the word line WL1 in the second memory cell array B2, all of the memory cells which can be actuated by this word line are conductively connected to the bit lines which are connected to them. This applies a voltage signal to all bit lines in the second memory cell array. All other memory cell arrays remain in the deactivated state.
In the deactivated state, the bit lines need to be charged to a common uniform voltage level as quickly as possible during a precharging process, in order to allow fresh access to the same memory cell array after the shortest possible time period. This prevents any influence during a fresh access operation by a random potential state on the bit lines, for example on account of a previous read access operation.
To clarify the way in which the circuit elements involved in a precharging process work, the circuit component IES (shown in dashed lines in FIG. 2), which is based on the prior art, is shown in an enlarged view in FIG. 3. FIG. 3 shows the sense amplifier SA in the sense amplifier strip SFa, which is connected to the bit line BL or to the complementary bit line /BL in the second memory cell array B2 via the two switching transistors ISO1 and ISO2. During access to the second memory cell array B2, the transistors ISO1 and ISO2 are turned on by applying the control signal MUX1 to their common control connection MA1. The bit line BL and the complementary bit line /BL in the second memory cell array are conductively connected to the sense amplifier SA in this case. The bit lines BL and /BL can also be connected to one another by means of a first switching transistor ET1. In addition, a second switching transistor ET2 and the transistor LT acting as a current limiter connect the bit line BL to the connection A10 for applying the mid-voltage VBLEQ. A third switching transistor ET3 and the transistor LT for current limiting likewise connect the complementary bit line /BL to the connection A10 for applying the mid-voltage VBLEQ. In this case, the mid-voltage VBLEQ is in the form of a voltage level between a high voltage level VBLH and a low voltage level VBLL. The high voltage level VBLH corresponds to the logic 1 information item and the low charge level VBLL corresponds to the logic 0 information item in this case. The two switching transistors ET2 and ET3 are connected to one another via a common connection Z. The three switching transistors ET1, ET2 and ET3 can be controlled by applying a control signal EQL to a common control connection EA. The transistor for current limiting LT can be controlled by applying a control signal SL to its control connection S10.
The precharging process generally takes place after a read or write access operation. To this end, the switching transistors ET1, ET2 and ET3 are turned on by applying the control signal EQL to their common control connection EA. At the same time, the transistor LT for current limiting is also turned on by applying the control signal SL to its control connection S10. The bit line BL and the complementary bit line /BL are connected to one another by means of the first switching transistor ET1, which is on. In addition, the second switching transistor ET2 and the transistor LT for current limiting connect the bit line BL to the connection A10 for applying the mid-voltage VBLEQ. Similarly, the transistor LT for current limiting and the third switching transistor ET3 connect the complementary bit line /BL to the connection A10 for applying the mid-voltage VBLEQ. The connection of the bit line BL and the complementary bit line /BL to the connection A10 for applying the mid-voltage VBLEQ and also the connection of the bit line BL and the complementary bit line /BL via the first switching transistor ET1, which is on, mean that a common equalization potential which corresponds to the mid-voltage VBLEQ will appear on the two bit lines.
FIGS. 4A to 4C illustrate the voltage states on the bit lines BL and /BL while the bit lines are being precharged to the mid-voltage VBLEQ. FIG. 4A shows four sense amplifiers SA1, SA2, SA3 and SA4 which are respectively connected to a bit line pair which includes the two bit lines BL and /BL. The fact that the bit line pairs are adjacent to one another at a short physical distance and also the small feature widths of the individual bit lines mean that the bit line pairs are capacitively coupled to one another. In addition, the complementary bit line /BL connected to the first sense amplifier SA1 is capacitively coupled via a first parasitic coupling capacitor CK1 to the bit line BL which is connected to the second sense amplifier SA2. The complementary bit line /BL connected to the second sense amplifier SA2 is connected via a second parasitic coupling capacitor CK2 to the bit line BL which is connected to the third sense amplifier SA3. The complementary bit line /BL connected to the third sense amplifier SA3 is connected via a third parasitic coupling capacitor CK3 to the bit line BL which is connected to the fourth sense amplifier SA4. By activating the word line WL, the memory cells SZ connected to the bit lines are applied to the bit lines, and the information stored in them is amplified. In the example in FIG. 4A, the bit lines denoted by “0” have memory cells SZ connected to them that store a logic 0 information item. The bit lines denoted by “1” have memory cells connected to them which store a logic 1 information item. When the memory cells SZ connected to the bit lines BL and /BL are read, the bit lines denoted by “0” assume the low voltage level VBLL, for example 0V, and the bit lines denoted by “1” assume the high voltage level VBLH, for example 1.5 V.
The low voltage potential on the complementary bit line /BL connected to the second sense amplifier SA2 and the high voltage potential on the bit line BL connected to the third sense amplifier SA3 charge the second parasitic coupling capacitor CK2 to a high voltage level of, by way of example, 1.5 V, which corresponds to the voltage level VBLH. The charge stored on the second parasitic coupling capacitor CK2 produces a voltage offset on the complementary bit line /BL connected to the second sense amplifier SA2, which bit line has been charged to the low voltage level VBLL. Similarly, a voltage shift is produced on the bit line BL which is connected to the third sense amplifier SA3.
FIG. 4B shows the voltage potential on the bit lines BL and /BL connected to the sense amplifier SA2 during a read access operation and a subsequent precharging process. Assuming that the memory cell SZ connected to the bit line BL stores a logic 1 information item, the bit line BL is charged to the high voltage level VBLH during a read access operation up to the time TP. Conversely, the complementary bit line assumes the low voltage level VBLL, corresponding to the logic 0 information item. At the time TP, the bit line BL and the complementary bit line /BL are conductively connected via the switching transistor ET1 shown in FIG. 3. The common voltage potential which is then put on the bit line pair is a potential VO, which is below the mid-voltage VBLEQ on account of the negative offset voltage on the bit line /BL.
FIG. 4C shows the voltage potential on the bit lines BL and /BL connected to the sense amplifier SA3 during a read access operation and a subsequent precharging process. During the read access operation, the bit line BL is charged to the high voltage level VBLH, which corresponds to the logic 1 information item. The complementary bit line has assumed the low voltage level VBLL, which corresponds to the logic 0 information item. At the time TP, the precharging process starts. The bit line BL and the complementary bit line /BL are connected via the first switching transistor ET1 shown in FIG. 3, which is on. The common voltage potential which is then put on the bit line pair is a potential VO, which is above the mid-voltage VBLEQ on account of the positive offset voltage on the bit line BL.
Since, as FIG. 3 shows, the current limiter transistor LT and the second switching transistor ET2 connect the bit line BL, and the current limiter transistor LT and the third switching transistor ET3 connect the complementary bit line /BL, to the connection A10 for applying the mid-voltage VBLEQ, the common voltage potential which appears on the bit line pair after the time TA has elapsed will be the potential VBLEQ again. In FIG. 4B, the voltage potential on the bit line pair BL and /BL starts from a voltage offset VO which is below the mid-voltage and approaches the mid-voltage VBLEQ. In FIG. 4C, the voltage potential on the bit line pair BL and /BL starts from a voltage offset VO which is above the mid-voltage and approaches the mid-voltage VBLEQ. The voltage VBLEQ connected to the connection A10 is between the high voltage potential VBLH, which corresponds to the logic 1 information item, and the low voltage potential VBLL, which corresponds to the logic 0 information item. Preferably, it corresponds to the arithmetic mean from the voltage VBLH and the voltage VBLL to which the bit line BL and the complementary bit line /BL are charged.
Referring again to FIG. 4A, no charges are stored on the first coupling capacitance CK1 and the third coupling capacitance CK3. The reason for this is that the first coupling capacitance CK1 connects two bit lines that are each charged to a voltage potential VBLH, which corresponds to the logic state 1. The coupling capacitance CK3 connects two bit lines which are each charged to the voltage potential VBLL, which corresponds to the logic state 0.
A voltage shift VO appears at the start of a precharging process only if one of the capacitively coupled bit lines has been charged using a high voltage potential and the other bit line has been charged using a low voltage potential. The time TA, as shown in FIGS. 4B and 4C, which is after the voltage potential VBLEQ (corresponding to the mean from the high and low voltage levels VBLH and VBLL) has appeared on the two bit lines, is generally in the range of about 100 ns (nanoseconds).
The charge stored on the coupling capacitances CK when the data topology is unfavorable produces a voltage offset on the bit lines which cannot be eliminated by shorting the bit lines through the first switching transistor ET1 (which is on). This charge can be dissipated only via the transistor for current limiting, which connects the bit line BL and the complementary bit line /BL to the connection A10 for applying the mid-voltage VBLEQ. The time TA which is required until the bit line BL and the complementary bit line /BL have been charged to the common voltage level VBLEQ is essentially dependent on the magnitude of the coupling capacitance CK, on the high voltage level VBLH which corresponds to the logic 1 information item and on the resistance of the transistor LT for current limiting.
The resistance of the transistor for current limiting determines the level of the equalization current draining to the connection A10. Its resistance can be altered by the control voltage which is applied to the control connection SL. In the exemplary embodiment in FIG. 3, a fixed internal voltage VINT is connected to the control connection SL of the transistor for current limiting, where the fixed internal voltage corresponds to the threshold voltage of the transistor for current limiting at room temperature (e.g., about 25° C.). When the integrated semiconductor memory device is operated in the low temperature range, the threshold voltage of the transistor for current limiting is generally increased.
If the transistor for current limiting is turned on by actuating its control connection with the constant control signal SL (e.g., the constant control voltage VINT), the transistor is turned on inadequately, particularly at low temperatures. This means that the resistance of the transistor for current limiting is too high to dissipate the charge stored on the coupling capacitance CK to the connection A10 in the prescribed precharging time. The time TA which is needed in order to charge the bit line BL and the complementary bit line /BL to the common voltage potential VBLEQ from the start of the precharging process to the time TP is in this case longer than the available precharging time. Since it is no longer possible to assume the desired equalization potential VBLEQ within the available precharging time, increased failures arise, particularly when the integrated semiconductor memory device is operated at a low temperature. To minimize such failures, the integrated semiconductor memories are currently tested using a coupling-critical data topology and a reduced precharging time. However, the stringent test conditions in turn result in an increased loss of yield during the test phase.